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業(yè)務(wù)單元
Telecom Board信息
  • Board Size: 11.2” * 4.9”
  • Number of Nodes: 3083
  • Accessible Nodes: 1827
  • Number of Components: 1915
  • Number of Boundary-Scan Test: 9
  • Number of On-board-programming: 2
  • Lowest Voltage Level: 1.1 V
 
挑戰(zhàn)與對(duì)策
  • 挑戰(zhàn)一
    • Total 11 Power Buses(Include external power supply input and board internal generated)
    • Power on safety and stability make sure
  • 我們的方案
    • Design test strategy for powered test
      • Correct power supply point and power up sequence
      • Crucial Fixture circuit and wiring for power up (current flow capability and power sense feedback control consideration)
    • Design debug strategy
      • How to safely turn on each power
      • How to eliminate noise coming from fixture
 
 
  • 挑戰(zhàn)二
    • In_Line_Device_Programming
      • CPLD SVF PROGRAMMING(Device D15)
  • 我們的方案
    • Using terILDP_SVF_STAPL driver to program, SVF file format (original firmware format could be .pof,.jed,etc)
 
 
  • 挑戰(zhàn)三
    • 1Gbit BOOT FLASH PROGRAMING(Device D5)
  • 我們的方案
    • Using CC3 Flash2 drive, to implement Fast programming, approach to datasheet theoretical programming time(Device D5)
    • Spilt the firmware to resolve maximum programming timeout of tester VP card
    • Program dynamic data to memory, such as MAC address or board serial number, etc
 
 
  • 挑戰(zhàn)四
    • Board contain 2 single BS ICs plus 2 BS chains
      • D1(Single Device,MPC8548V)
      • D15(single Device, CPLD)
      • CHAIN1:D9->D10->D20
      • CHAIN2:D16->D18->D19->D28
  • 我們的方案
    • Using Powerful victory software to generate great vector pattern to check every accessible pin of BS ICs compliance with IEEE1149.1 std
    • Work with accurate boundary scan intelligent diagnostic, quickly positioning and re-work product defects
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